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--- hardware:audio [2023/08/23 02:01] – created clyde
+++ hardware:audio [2025/03/01 20:39] (current) – [Effective sample rate] clyde
@@ Line 5: / Line 5: @@
 The ACP consists of a 65C02 processor, a 4K dual-ported RAM that is shared with the main system's memory map, a programmable timer that triggers the 65C02's IRQ at regular intervals, an 8-bit DAC, and a buffer register.
-===== Audio RAM =====
+==== Audio RAM ====
 The 4K dual-ported RAM encompasses the entirety of the memory that the ACP can address. The memory range $0000-$0FFF maps to the RAM and address above that will cycle over that range.
 The same memory can be accessed by the main system's processor between addresses $3000-$3FFF, utilizing the second port of the SRAM.
+Both systems can access this memory at the same time, therefore care should be taken to not write to the same location from both sides simultaneously, or perform a simultaneous read and write that may have unpredictable results.
+==== The IRQ Generator ====
+The ACP's programmable timer is used for triggering interrupts on the 65C02. This simplifies the task of making sure that audio samples are being emitted at a steady rate regardless of the complexity of the audio program.
+==== The DAC ====
+The digital-to-analog-converter controls the voltage level that is emitted on the audio jack.
+The DAC is not directly writable by the ACP. Any write by the ACP to an address at $8000 or above will also be mirrored to a buffer register. This buffer register is copied to the DAC at every IRQ signal.
+==== Audio Control Registers ====
+Write-only registers. $2000 and $2001 trigger on any write, regardless of value.
+^ Addr  ^ Use                                      ^
+| $2000 | Write to reset audio coprocessor.      |
+| $2001 | Write to send NMI to audio coprocessor |
+| $2006 | Audio enable and sample rate           |
+===== Programming =====
+==== Effective sample rate ====
+The IRQ timer determines the sample rate by setting how many cycles lapse between DAC updates. The number of cycles is equal to the value of the register times four, since the IRQ timer is clocked at the main CPU frequency while the audio processor clock runs four times as fast.
+The main CPU clock is the same as the NTSC color carrier frequency, approximately 3.5795Mhz or exactly 315/88 MHz. So the audio rate with the most cycles available will be 315000000/(256*88) = 13982 Hz
+Conversely the IRQ rate can go as high as 3.5795MHz but without time for any CPU operations this isn't very useful
+Here's a table with some example rate settings close to some commonly used sample rates
+^ Hex ^ Sample Rate (Hz)   ^ Closest Common Rate  ^  Difference ^ ACP cycles per sample ^
+| **$FF** | **13983** |  N/A (Lowest setting)  | N/A   | 1024 |
+| **$EF** | **15980** | 16000 | 19.9  | 896 |
+| **$D0** | **22233** | 22050 | 183.2 | 644 |
+| **$B7** | **31960** | 32000 | 39.8  | 448 |
+| **$A8** | **44192** | 44100 | 91.9  | 324 |
+| **$A5** | **47099** | 32000 | 900.7 :( | 304 |
+| **$94** | **87306** | 88200 | 894.0 :( | 164 |
+| **$92** | **96744** | 96000 | 744.5 :( | 148 |
+==== Initializing the audio system ====
+For consistent and predictable (i.e. "correct") behavior the program code should be written to the Audio RAM while the ACP is paused. Then before it is resumed, it should be sent a reset signal. If using the lowest audio rate described above, the process is as follows:
+  - Write zero to $2006, the audio rate register
+  - Copy program data to Audio RAM
+  - Write anything to $2000, the audio reset trigger
+  - Write 255 to $2006
+Whichever value you choose for audio rate, the highest bit of $2006 should be set to enable the ACP.
+Example ASM code:
+<code ASM>
+LDA #0
+STA $2006 ; audio rate/enable register
+JSR CopyMyAudioProgramIntoAudioRam
+LDA #0
+STA $2000 ; audio reset
+LDA #255
+STA $2006 ; 255 sets enable bit and lowest sample rate / highest cycles per sample
+</code>