Differences

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--- hardware:audio [2025/03/01 18:53] – clyde
+++ hardware:audio [2025/04/08 15:53] (current) – [The DAC] clyde
@@ Line 23: / Line 23: @@
 The DAC is not directly writable by the ACP. Any write by the ACP to an address at $8000 or above will also be mirrored to a buffer register. This buffer register is copied to the DAC at every IRQ signal.
+Sample bytes written to the DAC should be unsigned, where zero represents the lowest voltage it can output and 255 represents the highest.
 ==== Audio Control Registers ====
@@ Line 41: / Line 42: @@
 Conversely the IRQ rate can go as high as 3.5795MHz but without time for any CPU operations this isn't very useful
+Here's a table with some example rate settings close to some commonly used sample rates
+^ Hex ^ Sample Rate (Hz)   ^ Closest Common Rate  ^  Difference ^ ACP cycles per sample ^
+| **$FF** | **13983** |  N/A (Lowest setting)  | N/A   | 1024 |
+| **$EF** | **15980** | 16000 | 19.9  | 896 |
+| **$D0** | **22233** | 22050 | 183.2 | 644 |
+| **$B7** | **31960** | 32000 | 39.8  | 448 |
+| **$A8** | **44192** | 44100 | 91.9  | 324 |
+| **$A5** | **47099** | 32000 | 900.7 :( | 304 |
+| **$94** | **87306** | 88200 | 894.0 :( | 164 |
+| **$92** | **96744** | 96000 | 744.5 :( | 148 |
 ==== Initializing the audio system ====
@@ Line 52: / Line 66: @@
 Whichever value you choose for audio rate, the highest bit of $2006 should be set to enable the ACP.
+Example ASM code:
+<code ASM>
+LDA #0
+STA $2006 ; audio rate/enable register
+JSR CopyMyAudioProgramIntoAudioRam
+LDA #0
+STA $2000 ; audio reset
+LDA #255
+STA $2006 ; 255 sets enable bit and lowest sample rate / highest cycles per sample
+</code>