hardware:blitter
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hardware:blitter [2023/12/23 15:38] – [Blitter Registers] clyde | hardware:blitter [2024/09/06 19:13] (current) – clyde | ||
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The values of GX and GY last used by the Blitter will also influence which part of Sprite RAM the CPU can access in addition to the Banking Register. The video section of the memory map is only big enough for a 128x128 region. So the quadrant of Sprite RAM available to the CPU is determined by the most significant bit in the Sprite RAM coordinate counters. Typically these would be set before loading sprites by running a single-pixel blit operation copying from the target quadrant to an off-screen portion of the framebuffer. | The values of GX and GY last used by the Blitter will also influence which part of Sprite RAM the CPU can access in addition to the Banking Register. The video section of the memory map is only big enough for a 128x128 region. So the quadrant of Sprite RAM available to the CPU is determined by the most significant bit in the Sprite RAM coordinate counters. Typically these would be set before loading sprites by running a single-pixel blit operation copying from the target quadrant to an off-screen portion of the framebuffer. | ||
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+ | ===== Blitter Limits ===== | ||
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+ | Every blit takes the same number of cycles as pixels it covers, including skipped transparent pixels. | ||
+ | The blitter runs on the same clock as the CPU, which happens to be set at the NTSC colorburst frequency. | ||
+ | This can be calculated as exactly 315/88 MHz, or 315, | ||
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+ | However, this 59659 figure doesn' |
hardware/blitter.1703345938.txt.gz · Last modified: 2023/12/23 15:38 by clyde