Differences

This shows you the differences between two versions of the page.

--- hardware:flashcarts [2024/11/22 09:40] – clyde
+++ hardware:flashcarts [2025/11/16 03:25] (current) – dewbrite
@@ Line 1: / Line 1: @@
 ====== Flash Cartridges ======
+Cartridges connect to the GameTank's 36 pin cartridge port.
+===== Pinout =====
+{{ :hardware:cartridge_port_screenshot.png?600 |}}
+|1. +5V | 19. A13|
+|2. VIA PA2 | 20. _WRITE |
+|3. VIA PA7 | 21. _IRQ |
+|4. VIA PA1 | 22. A8 |
+|5. VIA PA0 | 23. A9 |
+|6. A12 | 24. A11 |
+|7. A7 | 25. _READ |
+|8. A6 | 26. A10 |
+|9. A5 | 27. _SEL |
+|10. A4 | 28. D7 |
+|11. A3 | 29. D6 |
+|12. A2 | 30. D5 |
+|13. A1 | 31. D4 |
+|14. A0 | 32. D3 |
+|15. D0 | 33. A14 |
+|16. D1 | 34. READY |
+|17. D2 | 35. _RESET |
+|18. CLK | 36. GND |
+==== Pinout Overview ====
+Cartridge memory is expected to be accessible through the address and data pins (A//x//, D//x//). These correspond _mostly_ to the CPU's address and data lines, notably for addresses 0x8000..=0xFFFF.
+The most significant bit is used for pin 27 (Cartridge Select), and as such, the cartridge perceives the aforementioned address space in the range of 0x0000..=0x7FFF through pins A0..=A14
+Pin 27 (Cartridge Select, active low) corresponds to the CPU's most significant address bit, NOT.
+Pins 25 and 20 (Read and Write, active low) corresponds to the CPU's r/w signals.
+Pin 21 (IRQ, active low) corresponds to the CPU's IRQ line.
+Pin 34 (Ready) is connected to the CPU's Ready line.
+Pin 18 (Clock) is connected to the CPU clock (~3.5MHz)
+Pins 2 to 5 correspond to VIA pins PA0, PA1, PA2, and PA7, and are expected to be customized per-cartridge.
+The truth of the matter is, you can kind of do //whatever you want// with most of these pins, so, go wild, but, there are a number of well-supported cartridges that you may find useful.
+====== 2M Cartridge (J.21) ======
 {{ :hardware:flashcart.jpg?200}}
-This page covers information about the 2MB Flash Cartridge for the GameTank.
 The cartridge is built around a M29F160FT55N3E2 parallel NOR flash, which has 2 megabytes of storage capacity.
@@ Line 12: / Line 60: @@
 Alongside the flash memory, the chip has a shift register connected to pins 2, 4, and 5 on the cartridge. This shift register may control the 7 most significant address bits on the flash. Specifically, it only controls those address bits when the CPU requests an address on the cartridge (A15 HIGH) but in the lower half of cartridge memory (A14 LOW). When an address on the upper half of cartridge memory (A14 HIGH) is requested, the 7 banked address bits are pulled HIGH.
+===== Writing to the flash chip =====
 ===== Interfacing with the shift register from software =====