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hardware:flashcarts [2025/11/15 21:11] – [Pinout Overview] dewbritehardware:flashcarts [2025/11/16 03:25] (current) dewbrite
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 Cartridges connect to the GameTank's 36 pin cartridge port. Cartridges connect to the GameTank's 36 pin cartridge port.
  
-====== Pinout ======+===== Pinout =====
  
 {{ :hardware:cartridge_port_screenshot.png?600 |}} {{ :hardware:cartridge_port_screenshot.png?600 |}}
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 |18. CLK | 36. GND | |18. CLK | 36. GND |
  
-====== Pinout Overview ======+==== Pinout Overview ====
  
  
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 The most significant bit is used for pin 27 (Cartridge Select), and as such, the cartridge perceives the aforementioned address space in the range of 0x0000..=0x7FFF through pins A0..=A14 The most significant bit is used for pin 27 (Cartridge Select), and as such, the cartridge perceives the aforementioned address space in the range of 0x0000..=0x7FFF through pins A0..=A14
  
-Pin 27 (Cartridge Select, active low) corresponds to the CPU's most significant address bit.+Pin 27 (Cartridge Select, active low) corresponds to the CPU's most significant address bit, NOT.
  
 Pins 25 and 20 (Read and Write, active low) corresponds to the CPU's r/w signals. Pins 25 and 20 (Read and Write, active low) corresponds to the CPU's r/w signals.
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 Alongside the flash memory, the chip has a shift register connected to pins 2, 4, and 5 on the cartridge. This shift register may control the 7 most significant address bits on the flash. Specifically, it only controls those address bits when the CPU requests an address on the cartridge (A15 HIGH) but in the lower half of cartridge memory (A14 LOW). When an address on the upper half of cartridge memory (A14 HIGH) is requested, the 7 banked address bits are pulled HIGH. Alongside the flash memory, the chip has a shift register connected to pins 2, 4, and 5 on the cartridge. This shift register may control the 7 most significant address bits on the flash. Specifically, it only controls those address bits when the CPU requests an address on the cartridge (A15 HIGH) but in the lower half of cartridge memory (A14 LOW). When an address on the upper half of cartridge memory (A14 HIGH) is requested, the 7 banked address bits are pulled HIGH.
 +
 +===== Writing to the flash chip =====
 +
 +
  
 ===== Interfacing with the shift register from software ===== ===== Interfacing with the shift register from software =====
hardware/flashcarts.1763241078.txt.gz · Last modified: 2025/11/15 21:11 by dewbrite