Differences

This shows you the differences between two versions of the page.

--- hardware:memorymap [2023/08/24 01:49] – Add lots of info clyde
+++ hardware:memorymap [2025/03/12 17:19] (current) – [System Control Registers] clyde
@@ Line 17: / Line 17: @@
 ===== General Purpose RAM =====
-The lowest 8,196 addresses provide general-purpose data storage. Data stored in this range will only be read and written by the main processor, without side effects.
+The lowest 8,192 addresses provide general-purpose data storage. Data stored in this range will only be read and written by the main processor, without side effects.
 Of special note within this section are the ranges $0000-$00FF, and $0100-$01FF, called the Zero Page and the Stack respectively. Addresses in the Zero Page can be accessed more quickly by special opcodes, and addresses in the stack are used by certain operations such as calling and returning from subroutines.
@@ Line 27: / Line 27: @@
 These locations are write-only, meaning that any attempts to read from these locations will essentially return a random value. On the physical hardware the data bus will have no component imparting any particular voltage, so any values returned will come from uncertain forces like radio static or the whims of inscrutable unseen entities.
-Addresses $2000, $2001, and $2006 are used for controlling the [[hardware:audio|Audio Coprocessor]].
+^ Addr  ^ Use                                      ^
+| $2005 | Banking Register                         |
+| $2007 | Video/Blitter Flags                      |
+==== Audio Coprocessor ===
+Addresses $2000, $2001, and $2006 are used for controlling the [[hardware:audio|Audio Coprocessor]]. The first two are used for triggering the RESET and NMI vectors respectively. The high bit of $2006 enables or disables the ACP. The lower seven bits determine the sample rate of the audio system by way of setting the number of clock cycles between the ACP receiving IRQ events. These are also write-only.
+^ Addr  ^ Use                                      ^
+| $2000 | Write to reset audio coprocessor       |
+| $2001 | Write to send NMI to audio coprocessor |
+| $2006 | Audio enable and sample rate           |
+$2000 and $2001 trigger on any write, regardless of value.
 ==== Banking Register ====
@@ Line 52: / Line 66: @@
 | 00001000 | DMA_COLORFILL_ENABLE | Use solid colors for blits instead of sprites                         |
 | 00010000 | DMA_GCARRY           | Set 0 to repeat 16x16 tiles on blit draws                             |
-| 00100000 | DMA_CPU_TO_VRAM      | 0 means CPU accesses Sprite RAM1 means the CPU access the framebuffer |
+| 00100000 | DMA_CPU_TO_VRAM      | 0 means CPU accesses Sprite RAM, 1 means the CPU access the framebuffer |
 | 01000000 | DMA_IRQ              | Enable IRQ signal when blits finish                                   |
 | 10000000 | DMA_OPAQUE           | Set 1 to disable transparency                                         |
@@ Line 62: / Line 76: @@
 A byte read from one of these locations will return 6 binary button states from the respective controller. Consecutive reads to the same port will toggle the "select" line on the controller port, causing the controller to change which six button states are being returned. More on reading gamepads can be found in its own article.
+^ Addr  ^ Use                                      ^
+| $2008 | Gamepad 1 (Left port)                    |
+| $2009 | Gamepad 2 (Right port)                   |
+===== Versatile Interface Adapter =====
+Addresses $2800-$280F map to the sixteen registers of the [[hardware:via|Versatile Interface Adapter]] or "VIA" for short.
+Addresses $2810-$2FFF will also map to the same sixteen registers.
+The VIA is used to control the "SPI" pins on the cartridge port as well as the general-purpose IO pins on the rear of the console. More detail is available on the specific VIA article.
+^ Addr  ^ Use                                      ^
+| $2800 | I/O Register B |
+| $2801 | I/O Register A |
+| $2802 | Data Direction Register B |
+| $2803 | Data Direction Register A |
+| $2804 | Timer 1 Low-Order Latches/Counter |
+| $2805 | Timer 1 High-Order Counter |
+| $2806 | Timer 1 Low-Order Latches |
+| $2807 | Timer 1 High-Order Latches |
+| $2808 | Timer 2 Low-Order Latches/Counter |
+| $2809 | Timer 2 High-Order Counter |
+| $280A | Shift Register |
+| $280B | Auxiliary Control Register |
+| $280C | Peripheral Control Register  |
+| $280D | Interrupt Flag Register  |
+| $280E | Interrupt Enable Register |
+| $280F | Same as Reg 1 except no "Handshake" |
+[[https://www.westerndesigncenter.com/wdc/documentation/w65c22.pdf|Manufacturer datasheet for W65C22 VIA]]
 ===== Audio RAM =====
@@ Line 71: / Line 116: @@
 [[graphics:memory|Video RAM]] is accessible from $4000-$7FFF and maps to either the Framebuffer, Sprite RAM, or the Blitter Parameters.
+===== Cartridge Slot =====
+The upper half of the GameTank's address space is given to whatever hardware sits in the cartridge slot. The highest address bit on the main bus is presented to the cartridge inverted as an active-low cartridge enable signal. When any address at $8000 or higher is accessed, the cartridge is responsible for further address decoding and activation of memory chips it has on board.
+==== EEPROM Cartridges ====
+Some of the simplest devices to go in the cartridge slot carry a single parallel EEPROM and a bypass capacitor. Any parallel EEPROM up to 32Kx8 can be used without additional banking hardware. Early cartridges for the GameTank used 8K EEPROMs.
+==== 2MB Flash Cartridges ====
+The typical cartridge used at time of writing has 2 megabytes of NOR flash and some extra chips to help access this data through a 32 kilobyte cartridge address space. See [[hardware:flashcarts|Flash Cartridges]] for more info.