hardware:memorymap
                Differences
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| Both sides previous revisionPrevious revisionNext revision | Previous revision | ||
| hardware:memorymap [2023/08/24 02:02] – clyde | hardware:memorymap [2025/03/12 17:19] (current) – [System Control Registers] clyde | ||
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| ===== General Purpose RAM ===== | ===== General Purpose RAM ===== | ||
| - | The lowest 8,196 addresses provide general-purpose data storage. Data stored in this range will only be read and written by the main processor, without side effects. | + | The lowest 8,192 addresses provide general-purpose data storage. Data stored in this range will only be read and written by the main processor, without side effects. | 
| Of special note within this section are the ranges $0000-$00FF, | Of special note within this section are the ranges $0000-$00FF, | ||
| Line 28: | Line 28: | ||
| ^ Addr ^ Use ^ | ^ Addr ^ Use ^ | ||
| - | | $2000 | Write 1 to reset audio coprocessor | ||
| - | | $2001 | Write 1 to send NMI to audio coprocessor | | ||
| | $2005 | Banking Register | | $2005 | Banking Register | ||
| - | | $2006 | Audio enable and sample rate | | ||
| | $2007 | Video/ | | $2007 | Video/ | ||
| - | | $2008 | Gamepad 1 (Left port) | | ||
| - | | $2009 | Gamepad 2 (Right port) | | ||
| - | |||
| ==== Audio Coprocessor === | ==== Audio Coprocessor === | ||
| - | Addresses $2000, $2001, and $2006 are used for controlling the [[hardware: | + | Addresses $2000, $2001, and $2006 are used for controlling the [[hardware: | 
| + | |||
| + | ^ Addr ^ Use ^ | ||
| + | | $2000 | Write to reset audio coprocessor | ||
| + | | $2001 | Write to send NMI to audio coprocessor | | ||
| + | | $2006 | Audio enable and sample rate | | ||
| + | |||
| + | $2000 and $2001 trigger on any write, regardless of value. | ||
| ==== Banking Register ==== | ==== Banking Register ==== | ||
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| | 00001000 | DMA_COLORFILL_ENABLE | Use solid colors for blits instead of sprites | | 00001000 | DMA_COLORFILL_ENABLE | Use solid colors for blits instead of sprites | ||
| | 00010000 | DMA_GCARRY | | 00010000 | DMA_GCARRY | ||
| - | | 00100000 | DMA_CPU_TO_VRAM | + | | 00100000 | DMA_CPU_TO_VRAM | 
| | 01000000 | DMA_IRQ | | 01000000 | DMA_IRQ | ||
| | 10000000 | DMA_OPAQUE | | 10000000 | DMA_OPAQUE | ||
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| The front [[hardware: | The front [[hardware: | ||
| A byte read from one of these locations will return 6 binary button states from the respective controller. Consecutive reads to the same port will toggle the " | A byte read from one of these locations will return 6 binary button states from the respective controller. Consecutive reads to the same port will toggle the " | ||
| + | |||
| + | ^ Addr ^ Use ^ | ||
| + | | $2008 | Gamepad 1 (Left port) | | ||
| + | | $2009 | Gamepad 2 (Right port) | | ||
| ===== Versatile Interface Adapter ===== | ===== Versatile Interface Adapter ===== | ||
| Line 82: | Line 88: | ||
| The VIA is used to control the " | The VIA is used to control the " | ||
| + | ^ Addr ^ Use ^ | ||
| + | | $2800 | I/O Register B | | ||
| + | | $2801 | I/O Register A | | ||
| + | | $2802 | Data Direction Register B | | ||
| + | | $2803 | Data Direction Register A | | ||
| + | | $2804 | Timer 1 Low-Order Latches/ | ||
| + | | $2805 | Timer 1 High-Order Counter | | ||
| + | | $2806 | Timer 1 Low-Order Latches | | ||
| + | | $2807 | Timer 1 High-Order Latches | | ||
| + | | $2808 | Timer 2 Low-Order Latches/ | ||
| + | | $2809 | Timer 2 High-Order Counter | | ||
| + | | $280A | Shift Register | | ||
| + | | $280B | Auxiliary Control Register | | ||
| + | | $280C | Peripheral Control Register | ||
| + | | $280D | Interrupt Flag Register | ||
| + | | $280E | Interrupt Enable Register | | ||
| + | | $280F | Same as Reg 1 except no " | ||
| + | |||
| + | [[https:// | ||
| ===== Audio RAM ===== | ===== Audio RAM ===== | ||
hardware/memorymap.1692842553.txt.gz · Last modified: 2023/08/24 02:02 by clyde
                
                