This page covers information about the 2MB Flash Cartridge for the GameTank.

The cartridge is built around a M29F160FT55N3E2 parallel NOR flash, which has 2 megabytes of storage capacity.

Since the 6502 is only able to address 64K of memory, and the GameTank cartridge slot is only afforded half of that range, a banking scheme is employed to access the full capacity of the flash chip.

The cartridge port only has 15 address bits, while the flash memory has 21. This means that 6 of the flash memory's address bits must be controlled by something other than the CPU's address outputs. Furthermore, since any banking hardware may be in an unknown state at boot there should be an address range that is unaffected by the banking state and thus becomes deterministic. Therefore an additional system address signal is reserved for requesting unbanked memory, and a total of 7 surplus flash address bits must be managed.

Alongside the flash memory, the chip has a shift register connected to pins 2, 4, and 5 on the cartridge. This shift register may control the 7 most significant address bits on the flash. Specifically, it only controls those address bits when the CPU requests an address on the cartridge (A15 HIGH) but in the lower half of cartridge memory (A14 LOW). When an address on the upper half of cartridge memory (A14 HIGH) is requested, the 7 banked address bits are pulled HIGH.

The pins connected to the shift register are controlled by the VIA, mapped to the lower 3 bits on Output Register A. Given that the respective bits of Data Direction Register A are configured for output mode, these bits on ORA can push a bank number into the shift register one bit at a time.

Each time CLOCK goes from 0 to 1, the value of DATA is pushed into the shift register. When LATCH goes from 0 to 1, the value of the shift register will take effect.